This invention relates generally to semiconductor integrated circuit devices and structures with polycrystal silicon or polycide wiring or interconnects in a lower or bottom layer of the structure and polycrystal silicon interconnects that embody a resistance in an upper layer of the structure and more particularly to the interconnect structure at the contact interface between a lower layer or interconnect and an upper layer or interconnect.
Integrated high resistance formation technology is an important process and technology characteristic in the design and manufacture of SRAM's. The current flowing in a formed high resistance need only be sufficient to compensate for transistor leakage, e.g., one order of magnitude or greater, and any current greater than such amount is unnecessary and only limits the application of the SRAM. Problems that provide limitations on such embodied resistance include: (1) maintenance of high resistance length, (2) polysilicon film thickness, (3) contamination by the impurities and (4) contamination of the passivation film by hydrogen.
Examples of the prior art are shown in FIGS. 3A to 3C and in FIGS. 4A to 4C. As shown in FIG. 3A, a LOCOS oxide film 32 and a gate oxide film 33, portions of which are removed by etching, are formed on a p-type single crystal Si substrate 31. Next, as shown in FIG. 3B, a polycrystal silicon layer is formed and a n.sup.+ diffusion is performed on the layer. After performing selective photoetching, the n.sup.+ polycrystal silicon interconnect 34 and n.sup.+ diffused layer 35 are formed.
As shown in FIG. 3C, ion implantation is performed and n.sup.+ diffusion of the source and drain is performed to form n.sup.+ diffusion layer 36. On top of that, an interlayer insulating film 37 is formed, a portion of which is removed by photoetching and a polycrystal silicon layer is formed which is partially treated with both ion implantation and photo etching to form the polycrystal silicon low resistance interconnect 39 which includes one or more high resistance regions 38.
In order to lower the wire resistance of resistance region 38 as much as possible, it is treated by ion implantation with large amounts of either arsenic or phosphorous. This technique has, however, two conflicting objectives of lowering the resistance of region 38 on one hand while raising the resistance as much as possible of another region on the other hand. As a result, (1) the polysilicon film thickness cannot be made sufficiently thin, (2) the resistance length of region 38 cannot be made sufficiently long in consideration of registration accuracy and (3) the diffusion of arsenic or phosphorous causes contamination so that resistance values as high as might be expected from the mask dimensions employed cannot in reality be obtained.
The following techniques have been implemented to solve these problems.
As shown in FIG. 4A, a LOCOS oxide film 42 is formed on the p-type single crystal Si substrate, and a gate oxide film 43 on substrate 41 is formed, a portion of which is removed by etching. As shown in FIG. 4B, a polycrystal silicon layer is formed after which a n.sup.+ diffusion and selective photoetching are performed to form the n.sup.+ polycrystal silicon interconnects 44 and n.sup.+ diffusion layer 45.
As illustrated in FIG. 4C, ion implantation is performed and n.sup.+ diffusion of the source and drain is performed to form the n.sup.+ diffusion layer 46. An interlayer insulation layer 47 is formed on top of layer 46, a portion of which is removed by etching. Next, a polycrystal silicon layer 50 is formed on top of layer 47 which is photoetched to form high resistance region 48. However, the heat produced during formation of polycrystal silicon layer 49 and in subsequent processing steps causes the phosphorus to infiltrate upwardly from lower layer polycrystal silicon interconnects 44 to form the n.sup.+ diffusion regions 49 in layer 50.
In this technique illustrated in FIG. 4, the high resistance polysilicon can, in principle, be made as thin as possible and no registration margin is required, so a longer high resistance length can be achieved compared to the case of the former technique of FIG. 3. However, even in the case of the technique of FIG. 4, phosphorus infiltrates from lower layer polysilicon interconnects 44 due to the heat, thus affecting or otherwise shortening the high resistance length. As memory densities on single chips have increased and the levels of integration and density have progressed with the state of the art, this phosphorus infiltration has become a serious problem in obtaining desired high resistance values.
It is an object of the present invention to prevent the infiltration of phosphorus from the lower layer polysilicon interconnect into a high resistance region in an upper or approximately located polysilicon interconnect to maintain the predesigned high resistance length of the high resistance region in the interconnect and thereby yielding an interconnect high resistance region capable of withstanding higher densities and higher levels of integration than presently possible in the prior art.